The first edition of Principles of Verifiable RTL Design  offered a common sense method for simplifying and unifying assertion  specification by creating a set of predefined specification modules  that could be instantiated within the designer's RTL. Since the  release of the first edition, an entire industry-wide initiative for  assertion specification has emerged based on ideas presented in the  first edition. This initiative, known as the Open Verification Library  Initiative (www.verificationlib.org), provides an assertion interface  standard that enables the design engineer to capture many interesting  properties of the design and precludes the need to introduce new HDL  constructs (i.e., extensions to Verilog are not required).  Furthermore, this standard enables the design engineer to `specify  once,' then target the same RTL assertion specification over multiple  verification processes, such as traditional simulation, semi-formal  and formal verification tools. The Open Verification Library  Initiative is an empowering technology that will benefit design and  verification engineers while providing unity to the EDA community  (e.g., providers of testbench generation tools, traditional  simulators, commercial assertion checking support tools, symbolic  simulation, and semi-formal and formal verification tools).   The second edition of Principles of Verifiable RTL Design  expands the discussion of assertion specification by including a new  chapter entitled `Coverage, Events and Assertions'. All assertions  exampled are aligned with the Open Verification Library Initiative  proposed standard. Furthermore, the second edition provides expanded  discussions on the following topics:   start-up  verification;    the place for 4-state simulation;    race  conditions;    RTL-style-synthesizable RTL (unambiguous mapping to  gates);    more `bad stuff'.       The goal of the second  edition is to keep the topic current. Principles of Verifiable RTL  Design, A Functional Coding Style Supporting Verification  Processes, Second Edition tells you how you can write Verilog to  describe chip designs at the RTL level in a manner that cooperates  with verification processes. This cooperation can return an order of  magnitude improvement in performance and capacity from tools such as  simulation and equivalence checkers. It reduces the labor costs of  coverage and formal model checking by facilitating communication  between the design engineer and the verification engineer. It also  orients the RTL style to provide more useful results from the overall  verification process.

Principles of Verifiable RTL Design 2nd Edition - A Functional Coding Style Supporting Verification Processes in Verilog PDF

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