There has been an increasing demand for Wireless Local Area  Network (WLAN) systems in the past few years. New frequency bands are  allocated and new standards are being developed to accommodate higher  data rates. The fast trend of CMOS scaling has provided an opportunity  for the development of low cost integrated WLAN systems.  Frequency synthesizers are one of the main building blocks of wireless  transceivers. The high frequency digital frequency dividers in a  phase-locked loop (PLL) based frequency synthesizer are among the most  challenging blocks to design and usually account for a large  percentage of the synthesizer total power dissipation. The successful  design and integration of a high frequency PLL demands a comprehensive  understanding of wireless systems, RF circuits, and loop stability  issues.  Multi-GHz Frequency Synthesis & Division starts with an overview  of WLAN systems and reviews the WLAN market and standards. It then  studies PLLs as an essential building block of WLAN receivers, and  provides guidelines and engineering recipes for the design of loop  filters in high frequency PLLs. Additionally, the book investigates  different analog and digital frequency division techniques and  introduces injection-locked frequency dividers (ILFDs) as an  alternative for conventional frequency dividers. Finally, the book  demonstrates a successful design of a fully integrated CMOS frequency  synthesizer for a 5 GHz WLAN receiver.  Multi-GHz Frequency Synthesis & Division will be of interest to  RF and high-speed analog circuit designers and students as well as  wireless engineers.

Multi-GHz Frequency Synthesis & Division PDF

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